ALU and FPU Design Patterns Over The Last Decade

Over the last decade we have been focusing on performance and power consumptions, whether it’s architecture complexity or time and space tradeoffs. Throughout the years we have managed to implement ALU designs that enable us to achieve faster running times, or cheaper production costs. Building a Pipelined Array Multipliers using 2-Dimensional Pipeline Gating has allowed us Simulation results averaging a power saving of 65% and latency reduction of 45%, or developing a system that allows for different frequencies to have an important effect on the power consumption such as implementing a clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. Keywords—Execution time, Floating Point Unit, Energy Consumption, ITRS technology Node, Datapath Width, power consumption, high scalability, CMOS technology.